1. Field of the Invention
The present invention relates to a wafer map analysis aid system and a wafer map analyzing method for analyzing various defects such as product failures caused in a semiconductor manufacturing process by using an image of a wafer map which is displayed on a monitor.
2. Description of the Background Art
In a semiconductor manufacturing line, a monitor wafer such as a bare wafer is used to check states of various manufacturing apparatus before a product lot is processed. More specifically, dummy operation of the manufacturing apparatus is performed to ascertain whether dust particles stick to a wafer for a test or not and to make a check on means of transportation, thereby confirming that the manufacturing apparatus is in a state suitable for manufacture. After the confirmation of the state, a predetermined number of product lots are manufactured. Numerical data obtained by the confirmation of the state of the apparatus and that obtained after the products are processed are utilized for quality control of the products by using a method such as statistical quality control. Examples of the numerical data include the number of dust particles sticking to a wafer, the number of defects generated on the wafer, dimensions of a pattern formed on the wafer, thicknesses of a film formed on the wafer, a measured value of mask alignment errors, impurity concentrations, resistances of the film formed on the wafer and the like.
Map data collected in the manufacturing line is required when it is doubtful whether a process of statistical quality control (SQC) is stable or not and when a wafer map and a chip are analyzed for lots having yields which are lower than a specified value. The cause of troubles are also analyzed by using data on electrical characteristics which are usually obtained after completion of manufacture or map data on a test result.
FIG. 7 is a conceptual view for explaining a structure of a wafer map analysis aid system according to the prior art. In FIG. 7, the reference numeral 10 denotes data on a manufacturing step, the reference numeral 11 denotes data on statistical quality control, the reference numeral 12 denotes map data, and the reference numeral 13 denotes data on section failure analysis. The data 10 on the manufacturing step includes numerical data measured at each manufacturing step in addition to a flow of manufacture. The flow of manufacture has a link corresponding to manufacture of each product at various steps such as a preprocessing step, a film forming step, a photolithographic step, an etching step, a defect inspecting step and the like. The data 10 on the manufacturing step is stored as a document, data of a computer and the like which are properly retrieved if necessary. The data 11 on the statistical quality control is processed and provided in simple form which is easy to see, for example, a graph. The map data 12 includes data on a test wafer which is used for apparatus management during dummy operation, data on a wafer which is extracted as a sample at an actual manufacturing step, and data obtained by performing various tests after a product is finished. Since the map data 12 represents various information on an image of the wafer, a data quantity is increased. The data 13 on the section failure analysis is related to an image of a wafer section which is observed by using a scanning electron microscope. The data 11 on the statistical quality control, the map data 12 and the like are also provided as documents and data of a computer.
FIG. 8 is a conceptual view showing an example of the relationship between a manufacturing step and a measuring apparatus. Steps ST1 to ST5 shown in FIG. 8 represent a preprocessing step, a film forming step, a photolithographic step, an etching step and a defect inspecting step. Dummy operation may be carried out at the film forming step before manufacture is started, thereby performing contamination inspection using a monitor wafer. An image 29 in a portion of the wafer to which dust particles have stuck is integrated as map data 19a. In some cases, the dummy operation is carried out at other steps.
After the film forming step ST2, a thickness of the formed film is measured to create map data 20a. For example, an image such as a wafer map 30 is obtained by the map data 20a. Similarly, a resist pattern and an etching pattern are measured or defect inspection is performed after the photolithographic step ST3, the etching step ST4 and the defect inspecting step ST5. Consequently, map data 21a to 23a are created. For example, images such as wafer maps 31 to 33 are obtained by using the map data 21a to 23a.
The wafer map analysis aid system according to the prior art serves to individually present the data 10 on the manufacturing step, the data 11 on the statistical quality control, the map data 12, the data 13 on the section failure analysis or the like only in the special case where it becomes clear after the manufacture that trouble occurred in the manufacturing step, stability of the step is doubtful or a lot having a lower yield than a specified value is generated.
The wafer map analysis aid system according to the prior art has the above-mentioned structure. Only numerical management is performed, and the map data and other text data such as events are not taken into consideration if defects are not caused. Therefore, the wafer map analysis aid system cannot fully function if the defects are not represented as numeric values on data.
In the case where numerical data on a test result are identical but numeric values of the data of which distribution on a wafer should normally be random have a distribution with a tendency, it is indicated that a possibility that trouble may occur in the near future is increased. If only the numerical management is performed, it is difficult to perform analysis for giving a warning of such a future possibility.
Furthermore, it is hard to analyze the extent of an influence on any device provided in the wafer by the statistical quality control using only numeric values. A factor of troubles cannot be grasped before failure analysis is performed. For this reason, the trouble which might be prevented if it is perceived in the middle of manufacture is missed so that all lots are involved in the trouble.